Re: Re: [PATCH 3/4] RISC-V: Add crypto vector machine descriptions

t). > ;; So the source operand should have LMUL >= 1. > >Reference patch: >https://gcc.gnu.org/pipermail/gcc-patches/2023-December/638869.html > >Currently, I don't have a solution to support highest-number overlap for vv >instruction. >Keep

Re: [PATCH 3/4] RISC-V: Add crypto vector machine descriptions

roup ;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not). ;; So the source operand should have LMUL >= 1. Reference patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/638869.html Currently, I don't have a soluti

[PATCH 3/4] RISC-V: Add crypto vector machine descriptions

This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new i