Re: [PATCH 3/3] RISC-V: load and store-lanes with SLP

2024-07-11 Thread Richard Biener
On Wed, 10 Jul 2024, Richard Sandiford wrote: > Richard Biener writes: > > The following is a prototype for how to represent load/store-lanes > > within SLP. I've for now settled with having a single load node > > with multiple permute nodes acting as selection, one for each loaded lane > > and

Re: [PATCH 3/3] RISC-V: load and store-lanes with SLP

2024-07-10 Thread Richard Sandiford
Richard Biener writes: > The following is a prototype for how to represent load/store-lanes > within SLP. I've for now settled with having a single load node > with multiple permute nodes acting as selection, one for each loaded lane > and a single store node fed from all stored lanes. For > >

[PATCH 3/3] RISC-V: load and store-lanes with SLP

2024-07-10 Thread Richard Biener
The following is a prototype for how to represent load/store-lanes within SLP. I've for now settled with having a single load node with multiple permute nodes acting as selection, one for each loaded lane and a single store node fed from all stored lanes. For for (int i = 0; i < 1024; ++i)

[PATCH 3/3] RISC-V: load and store-lanes with SLP

2024-07-09 Thread Richard Biener
As promised this is the rework of SLP load/store-lane support with a simpler representation. It builds ontop the load-permute lowering series which I've squashed to two patches (already tested separately in the CI yesterday). The load/store-permute work hasn't seen much testing, I hope the CI w