On 14 November 2014 10:46, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set): Add
> variant reading from memory and assembling to ld1.
>
> * config/aarch64/arm_neon.h (vld1_lane_f32, vld1_lane_f64,
> vld1_lane_p8,
> v
The vld1_lane intrinsic is currently implemented using inline asm. This patch
replaces that with a load and a straightforward use of vset_lane (this gives us
correct bigendian lane-flipping in a simple manner).
Naively this would produce assembler along the lines of (for vld1_lane_u8):
