.@gcc.gnu.org
>> Subject: Re: [PATCH 2/2]AArch64: support encoding integer immediates using
>> floating point moves
>>
>> Tamar Christina writes:
>> > Hi All,
>> >
>> > This patch extends our immediate SIMD generation cases to support
>>
Hi,
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, September 30, 2024 6:33 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH 2/2]AArch64: support enc
Richard Earnshaw
>> ; Marcus Shawcroft
>> ; ktkac...@gcc.gnu.org
>> Subject: Re: [PATCH 2/2]AArch64: support encoding integer immediates using
>> floating point moves
>>
>> Tamar Christina writes:
>> > Hi All,
>> >
>> > This patch
gcc.gnu.org
> Subject: Re: [PATCH 2/2]AArch64: support encoding integer immediates using
> floating point moves
>
> Tamar Christina writes:
> > Hi All,
> >
> > This patch extends our immediate SIMD generation cases to support generating
> > integer immediate
Tamar Christina writes:
> Hi All,
>
> This patch extends our immediate SIMD generation cases to support generating
> integer immediates using floating point operation if the integer immediate
> maps
> to an exact FP value.
>
> As an example:
>
> uint32x4_t f1() {
> return vdupq_n_u32(0x3f8000
Hi All,
This patch extends our immediate SIMD generation cases to support generating
integer immediates using floating point operation if the integer immediate maps
to an exact FP value.
As an example:
uint32x4_t f1() {
return vdupq_n_u32(0x3f80);
}
currently generates:
f1:
adr
