Please update the commit message to reflect this.
On Wed, 15 Jun 2022 at 10:56, Christoph Müllner
wrote:
>
> On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
> wrote:
> >
> > On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> > wrote:
> > >
> > > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellne
On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
wrote:
>
> On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> wrote:
> >
> > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> > wrote:
> > >
> > > From: Christoph Müllner
> > >
> > > This adds Allwinner's D1 to the list of known cores.
> > > T
On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
wrote:
>
> On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This adds Allwinner's D1 to the list of known cores.
> > The Allwinner includes a single-core XuanTie C906 and is available
> > for quite
On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This adds Allwinner's D1 to the list of known cores.
> The Allwinner includes a single-core XuanTie C906 and is available
> for quite some time. Note, that the tuning struct for the C906
> is already part of
From: Christoph Müllner
This adds Allwinner's D1 to the list of known cores.
The Allwinner includes a single-core XuanTie C906 and is available
for quite some time. Note, that the tuning struct for the C906
is already part of GCC.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_COR