Re: [PATCH 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn

2024-06-12 Thread Edwin Lu
On 6/12/2024 12:39 AM, Robin Dapp wrote: Hi Edwin, this LGTM but I just remembered I intended to turn the assert into a more descriptive error. The attached patch has been sitting on my local branch for a while. Maybe we should rather fold yours into it? That's fine with me! Having more desc

Re: [PATCH 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn

2024-06-12 Thread Robin Dapp
Hi Edwin, this LGTM but I just remembered I intended to turn the assert into a more descriptive error. The attached patch has been sitting on my local branch for a while. Maybe we should rather fold yours into it? Regards Robin >From d164403ef577917f905c1690f2199fab330f05e2 Mon Sep 17 00:00:0

[PATCH 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn

2024-06-11 Thread Edwin Lu
When emitting insns, we have an early assertion to ensure the input operand's mode and the expanded operand's mode are the same; however, it does not perform this check if the pattern does not have an explicit machine mode specifying the operand. In this scenario, it will always assume that mode =