Could you CC to me ? I can't reply that patch directly.
juzhe.zh...@rivai.ai
From: Bohan Lei
Date: 2024-09-12 10:38
To: Bohan Lei
CC: gcc-patches; juzhe.zhong
Subject: RE: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused
An updated version has been submitted:
https://gcc.gn
An updated version has been submitted:
https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662854.html
--
From:Bohan Lei
Send Time:2024 Sep. 11 (Wed.) 17:12
To:"gcc-patches"
Subject:[PATCH 2/2] RISC-V: Eliminate lat
Hi Juzhe,
> Could you show me what the codegen looks like after this patch ?> I would be
> expecting the codegen become:
>
> foo:
> vsetvli a5,a0,e16,m1,ta,ma
> vmv.x.s a4,v8
> vadd.vx v9,v8,a4
> vsetvli zero,a5,e16,m1,ta,ma
> vadd.vv v8,v9,v8
> re
juzhe.zh...@rivai.ai
Subject: FW: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused
FYI
-Original Message-
From: Bohan Lei
Sent: Wednesday, September 11, 2024 5:13 PM
To: gcc-patches
Subject: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused
The current vsetvl pass eliminat
The current vsetvl pass eliminates a vsetvl instruction when the previous
info is "available," but does not when "compatible." This can lead to not
only redundancy, but also incorrect behaviors when the previous info happens
to be compatible with a later vector instruction, which ends of using the
