subject:"\[PATCH 2\/2\] RISC\-V\: Add testcases for signed vector SAT_ADD IMM form 1"

RE: [PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1

2025-04-25 Thread Li, Pan2

<--- here. Pan -Original Message- From: Li Xu Sent: Thursday, January 2, 2025 4:04 PM To: gcc-patches@gcc.gnu.org Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com; rdapp@gmail.com; xuli Sub

[PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1

2025-01-02 Thread Li Xu

From: xuli This patch adds testcase for form1, as shown below: void __attribute__((noinline)) \ vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \ {\ unsigned i;