Re: [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Hi Mary: Several inline comments, mostly are related to the RTX pattern. I guess we don't really need those unspec except clip*. > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index 59aeafe485f..30c8bcbe476 100644 > --- a/gcc/config/riscv/corev.md > +++ b/gcc/config/riscv/

[PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc