From: oluade01
This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(vec_widen_abdl_lo_, vec_widen_abdl_hi_):
Expansions for abd vec widen optabs.
(aarch64_abdl_insn): VQW based abdl RTL.
* confi
> Sorry, my fault, but I meant the comment about avoiding
> (minus (max…) (min…)) for both patterns, not just the first.
Change made.
> I think the review suggestions for 1/2 will change the tests.
> For example:
>
> TEST2(signed, short, char)
This is the case and the tests have been updated to
Oluwatamilore Adebayo writes:
> From: oluade01
>
> This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (vec_widen_abdl_lo_, vec_widen_abdl_hi_):
> Expansions for abd vec widen optabs.
> (aarch64_abdl_in
From: oluade01
This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(vec_widen_abdl_lo_, vec_widen_abdl_hi_):
Expansions for abd vec widen optabs.
(aarch64_abdl_insn): VQW based abdl RTL.
* confi
> > +(define_insn "aarch64_abdl_hi_internal"
> > + [(set (match_operand: 0 "register_operand" "=w")
> > + (minus:
> > + (USMAX:
> > + (:
> > + (vec_select:
> > + (match_operand:VQW 1 "register_operand" "w")
> > + (match_operand:VQW 3 "vect_par_cnst_hi_half"
Oluwatamilore Adebayo writes:
> From: oluade01
>
> This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (vec_widen_abdl_lo_, vec_widen_abdl_hi_):
> Expansions for abd vec widen optabs.
> (aarch64_abdl_in
From: oluade01
This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2).
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(vec_widen_abdl_lo_, vec_widen_abdl_hi_):
Expansions for abd vec widen optabs.
(aarch64_abdl_insn): VQW based abdl RTL.
* confi
