Richard Biener writes:
> On Thu, Sep 20, 2018 at 3:40 PM Richard Sandiford
> wrote:
>>
>> Richard Biener writes:
>> > On Mon, Sep 17, 2018 at 2:40 PM Andrew Stubbs
>> > wrote:
>> >> On 17/09/18 12:43, Richard Sandiford wrote:
>> >> > OK, sounds like the cost of vec_construct is too low then.
On Thu, Sep 20, 2018 at 3:40 PM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Mon, Sep 17, 2018 at 2:40 PM Andrew Stubbs wrote:
> >> On 17/09/18 12:43, Richard Sandiford wrote:
> >> > OK, sounds like the cost of vec_construct is too low then. But looking
> >> > at the port, I see y
Richard Biener writes:
> On Mon, Sep 17, 2018 at 2:40 PM Andrew Stubbs wrote:
>> On 17/09/18 12:43, Richard Sandiford wrote:
>> > OK, sounds like the cost of vec_construct is too low then. But looking
>> > at the port, I see you have:
>> >
>> > /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZATION
On Mon, Sep 17, 2018 at 2:40 PM Andrew Stubbs wrote:
>
> On 17/09/18 12:43, Richard Sandiford wrote:
> > OK, sounds like the cost of vec_construct is too low then. But looking
> > at the port, I see you have:
> >
> > /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST. */
> >
> > int
> > gc
On 17/09/18 12:43, Richard Sandiford wrote:
OK, sounds like the cost of vec_construct is too low then. But looking
at the port, I see you have:
/* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST. */
int
gcn_vectorization_cost (enum vect_cost_for_stmt ARG_UNUSED (type_of_cost),
Andrew Stubbs writes:
> On 17/09/18 10:14, Richard Sandiford wrote:
>> writes:
>>> If the autovectorizer tries to load a GCN 64-lane vector elementwise then it
>>> blows away the register file and produces horrible code.
>>
>> Do all the registers really need to be live at once, or is it "just"
On 17/09/18 10:14, Richard Sandiford wrote:
writes:
If the autovectorizer tries to load a GCN 64-lane vector elementwise then it
blows away the register file and produces horrible code.
Do all the registers really need to be live at once, or is it "just" bad
scheduling? I'd have expected the
writes:
> If the autovectorizer tries to load a GCN 64-lane vector elementwise then it
> blows away the register file and produces horrible code.
Do all the registers really need to be live at once, or is it "just" bad
scheduling? I'd have expected the initial rtl to load each element and
then i
If the autovectorizer tries to load a GCN 64-lane vector elementwise then it
blows away the register file and produces horrible code.
This patch simply disallows elementwise loads for such large vectors. Is there
a better way to disable this in the middle-end?
2018-09-05 Julian Brown
