> -Original Message-
> From: Kyrylo Tkachov
> Sent: Monday, July 7, 2025 11:16 AM
> To: GCC Patches
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Alex Coplan ; Andrew
> Pinski
> Subject: [PATCH 1/7] aarch64: Allow 64-bit vector modes in pattern for BCAX
&
Hi all,
The BCAX instruction from TARGET_SHA3 only operates on the full .16b form
of the inputs but as it's a pure bitwise operation we can use it for the 64-bit
modes as well as there we don't care about the upper 64 bits. This patch extends
the relevant pattern in aarch64-simd.md to accept the 6
