Ping.
Any comments on this?
The one line summary is that using self sets instead of clobber high would
result in a
patch roughly the same, but with different condition checks.
It depends if people think it really is useful for self sets to not be live.
Given that we are at stage 4 now, and this c
> On 19 Dec 2017, at 16:27, Jeff Law wrote:
>
> On 12/19/2017 03:12 AM, Alan Hayward wrote:
>> Ping ping.
>> I think there should be enough information in the first test to show that
>> any "set to self”
>> registers become live. Let me know if there’s anything I’ve missed.
> I think that both
On 12/19/2017 03:12 AM, Alan Hayward wrote:
> Ping ping.
> I think there should be enough information in the first test to show that any
> "set to self”
> registers become live. Let me know if there’s anything I’ve missed.
I think that both Richi and I would like you investigate fixing the df
infr
Ping ping.
I think there should be enough information in the first test to show that any
"set to self”
registers become live. Let me know if there’s anything I’ve missed.
Thanks,
Alan.
> On 12 Dec 2017, at 11:11, Alan Hayward wrote:
>
> Ping.
>
>> On 30 Nov 2017, at 11:03, Alan Hayward wrot
Ping.
> On 30 Nov 2017, at 11:03, Alan Hayward wrote:
>
>
>> On 27 Nov 2017, at 17:29, Jeff Law wrote:
>>
>> On 11/23/2017 04:11 AM, Alan Hayward wrote:
>>>
On 22 Nov 2017, at 17:33, Jeff Law wrote:
On 11/22/2017 04:31 AM, Alan Hayward wrote:
>
>> On 21 Nov 2017, at
> On 27 Nov 2017, at 17:29, Jeff Law wrote:
>
> On 11/23/2017 04:11 AM, Alan Hayward wrote:
>>
>>> On 22 Nov 2017, at 17:33, Jeff Law wrote:
>>>
>>> On 11/22/2017 04:31 AM, Alan Hayward wrote:
> On 21 Nov 2017, at 03:13, Jeff Law wrote:
>>
>>>
>>> You might also look
On 11/28/2017 04:55 AM, Richard Biener wrote:
>>> Or consider a stream of code containing two tls_desc calls (ok, the
>>> compiler might
>>> optimise one of the tls calls away, but this approach should be reusable
>>> for other exprs).
>>> Between the two set(x,x)’s x is considered live so the r
On Mon, Nov 27, 2017 at 6:29 PM, Jeff Law wrote:
> On 11/23/2017 04:11 AM, Alan Hayward wrote:
>>
>>> On 22 Nov 2017, at 17:33, Jeff Law wrote:
>>>
>>> On 11/22/2017 04:31 AM, Alan Hayward wrote:
> On 21 Nov 2017, at 03:13, Jeff Law wrote:
>>
>>>
>>> You might also look at T
On 11/23/2017 04:11 AM, Alan Hayward wrote:
>
>> On 22 Nov 2017, at 17:33, Jeff Law wrote:
>>
>> On 11/22/2017 04:31 AM, Alan Hayward wrote:
>>>
On 21 Nov 2017, at 03:13, Jeff Law wrote:
>
>>
>> You might also look at TARGET_HARD_REGNO_CALL_PART_CLOBBERED. I'd
>> totally fo
> On 22 Nov 2017, at 17:33, Jeff Law wrote:
>
> On 11/22/2017 04:31 AM, Alan Hayward wrote:
>>
>>> On 21 Nov 2017, at 03:13, Jeff Law wrote:
>
> You might also look at TARGET_HARD_REGNO_CALL_PART_CLOBBERED. I'd
> totally forgotten about it. And in fact it seems to come pre
On 11/22/2017 04:31 AM, Alan Hayward wrote:
>
>> On 21 Nov 2017, at 03:13, Jeff Law wrote:
>>>
You might also look at TARGET_HARD_REGNO_CALL_PART_CLOBBERED. I'd
totally forgotten about it. And in fact it seems to come pretty close
to what you need…
>>>
>>> Yes, some of the c
> On 21 Nov 2017, at 03:13, Jeff Law wrote:
>>
>>>
>>> You might also look at TARGET_HARD_REGNO_CALL_PART_CLOBBERED. I'd
>>> totally forgotten about it. And in fact it seems to come pretty close
>>> to what you need…
>>
>> Yes, some of the code is similar to the way
>> TARGET_HARD_REGNO_CALL
On 11/20/2017 08:04 AM, Alan Hayward wrote:
>>>
>>> Yes, that was an early alternative option for the patch.
>>>
>>> With that it would effect every operation that uses SVE registers. A simple
>>> add of two registers now has 4 inputs and two outputs. It would get in the
>>> way when debugging any
> On 17 Nov 2017, at 19:31, Jeff Law wrote:
>
> On 11/16/2017 11:50 AM, Alan Hayward wrote:
>>
>>> On 16 Nov 2017, at 18:24, Richard Biener wrote:
>>>
>>> On November 16, 2017 7:05:30 PM GMT+01:00, Jeff Law wrote:
On 11/16/2017 05:34 AM, Alan Hayward wrote:
> This is a set of patche
On 11/16/2017 11:50 AM, Alan Hayward wrote:
>
>> On 16 Nov 2017, at 18:24, Richard Biener wrote:
>>
>> On November 16, 2017 7:05:30 PM GMT+01:00, Jeff Law wrote:
>>> On 11/16/2017 05:34 AM, Alan Hayward wrote:
This is a set of patches aimed at supporting aarch64 SVE register
preservati
> On 16 Nov 2017, at 18:24, Richard Biener wrote:
>
> On November 16, 2017 7:05:30 PM GMT+01:00, Jeff Law wrote:
>> On 11/16/2017 05:34 AM, Alan Hayward wrote:
>>> This is a set of patches aimed at supporting aarch64 SVE register
>>> preservation around TLS calls.
>>>
>>> Across a TLS call, Aa
On November 16, 2017 7:05:30 PM GMT+01:00, Jeff Law wrote:
>On 11/16/2017 05:34 AM, Alan Hayward wrote:
>> This is a set of patches aimed at supporting aarch64 SVE register
>> preservation around TLS calls.
>>
>> Across a TLS call, Aarch64 SVE does not explicitly preserve the
>> SVE vector regist
On 11/16/2017 05:34 AM, Alan Hayward wrote:
> This is a set of patches aimed at supporting aarch64 SVE register
> preservation around TLS calls.
>
> Across a TLS call, Aarch64 SVE does not explicitly preserve the
> SVE vector registers. However, the Neon vector registers are preserved.
> Due to ov
This is a set of patches aimed at supporting aarch64 SVE register
preservation around TLS calls.
Across a TLS call, Aarch64 SVE does not explicitly preserve the
SVE vector registers. However, the Neon vector registers are preserved.
Due to overlapping of registers, this means the lower 128bits of
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