Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

2023-11-09 Thread Jeff Law
On 11/8/23 04:09, Mary Bennett wrote: +;; XCVELW builtins +(define_insn "riscv_cv_elw_elw_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))] + UNSPECV_CV_ELW))] + + "TARGET_XCVELW && !TARGET_64BIT" + "cv.elw\t

[PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

2023-11-08 Thread Mary Bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/