> > > From: Tamar Christina
> > > Sent: Wednesday, June 8, 2022 3:49 PM
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: nd ; Richard Earnshaw
> ;
> > > Marcus Shawcroft ; Kyrylo Tkachov
> > > ; Richard Sandiford
> > >
> > > Subject
; > Cc: nd ; Richard Earnshaw ;
> > Marcus Shawcroft ; Kyrylo Tkachov
> > ; Richard Sandiford
> >
> > Subject: [PATCH 1/2]AArch64 Fix 128-bit sequential consistency atomic
> > operations.
> >
> > Hi All,
> >
> > The AArch64 implementation of 128-bit
; ; Richard Sandiford
>
> Subject: [PATCH 1/2]AArch64 Fix 128-bit sequential consistency atomic
> operations.
>
> Hi All,
>
> The AArch64 implementation of 128-bit atomics is broken.
>
> For 128-bit atomics we rely on pthread barriers to correct guard the address
> in the p
ping
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, June 8, 2022 3:49 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: [PATCH 1/2]AArch64 Fix 128-bit se
Hi All,
The AArch64 implementation of 128-bit atomics is broken.
For 128-bit atomics we rely on pthread barriers to correct guard the address
in the pointer to get correct memory ordering. However for 128-bit atomics the
address under the lock is different from the original pointer.
This means
