Segher Boessenkool writes:
> On Mon, Sep 05, 2022 at 02:25:29PM +0800, Jiufu Guo wrote:
>> > On Fri, Sep 02, 2022 at 02:56:21PM +0800, Jiufu Guo wrote:
>> > Or force the testcase to use r0 some other way. Well, "forcing" cannot
>> > be done, but we can probably encourage it (via a local register
On Mon, Sep 05, 2022 at 02:25:29PM +0800, Jiufu Guo wrote:
> > On Fri, Sep 02, 2022 at 02:56:21PM +0800, Jiufu Guo wrote:
> > Or force the testcase to use r0 some other way. Well, "forcing" cannot
> > be done, but we can probably encourage it (via a local register asm for
> > example, or by tying
Hi,
Segher Boessenkool writes:
> Hi!
>
> On Fri, Sep 02, 2022 at 02:56:21PM +0800, Jiufu Guo wrote:
>> >> + /* pli 9,high32 + sldi 9,32 + paddi 9,9,low32. */
>> >> + else
>> >> + {
>> >
>> > The comment goes here, in the block it refers to. Comments for a block
>> > are the first thi
"Kewen.Lin" writes:
> Hi Jeff,
>
> Thanks for the patch, some comments on nits are inline.
>
> on 2022/9/1 11:24, Jiufu Guo wrote:
>> Hi,
>>
>> As mentioned in PR106550, since pli could support 34bits immediate, we could
>> use less instructions(3insn would be ok) to build 64bits constant with p
On Fri, Sep 02, 2022 at 10:29:35AM -0500, Peter Bergner wrote:
> On 9/1/22 4:52 PM, Segher Boessenkool wrote:
> > On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote:
> >> As mentioned in PR106550, since pli could support 34bits immediate, we
> >> could
> >> use less instructions(3insn would
Hi!
On Fri, Sep 02, 2022 at 02:56:21PM +0800, Jiufu Guo wrote:
> >> + /* pli 9,high32 + sldi 9,32 + paddi 9,9,low32. */
> >> + else
> >> + {
> >
> > The comment goes here, in the block it refers to. Comments for a block
> > are the first thing *in* the block.
> OK, great! I like the f
On 9/1/22 4:52 PM, Segher Boessenkool wrote:
> On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote:
>> As mentioned in PR106550, since pli could support 34bits immediate, we could
>> use less instructions(3insn would be ok) to build 64bits constant with pli.
>
>> For example, for constant 0x
Hi,
Segher Boessenkool writes:
> Hi!
>
> This patch is a clear improvement :-)
>
> On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote:
>> As mentioned in PR106550, since pli could support 34bits immediate, we could
>> use less instructions(3insn would be ok) to build 64bits constant wit
Hi Jeff,
Thanks for the patch, some comments on nits are inline.
on 2022/9/1 11:24, Jiufu Guo wrote:
> Hi,
>
> As mentioned in PR106550, since pli could support 34bits immediate, we could
> use less instructions(3insn would be ok) to build 64bits constant with pli.
>
> For example, for constant
Hi!
This patch is a clear improvement :-)
On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote:
> As mentioned in PR106550, since pli could support 34bits immediate, we could
> use less instructions(3insn would be ok) to build 64bits constant with pli.
> For example, for constant 0x02080500
Hi,
As mentioned in PR106550, since pli could support 34bits immediate, we could
use less instructions(3insn would be ok) to build 64bits constant with pli.
For example, for constant 0x020805006106003, we could generate it with:
asm code1:
pli 9,101736451 (0x6106003)
sldi 9,9,32
paddi 9,9, 213000
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