Spencer Abson writes:
> On Fri, Jun 06, 2025 at 10:02:19AM +0100, Richard Sandiford wrote:
>> Spencer Abson writes:
>> > @@ -27292,10 +27291,16 @@ aarch64_emit_sve_invert_fp_cond (rtx target,
>> > rtx_code code, rtx pred,
>> > void
>> > aarch64_expand_sve_vec_cmp_float (rtx target, rtx_code co
On Fri, Jun 06, 2025 at 10:02:19AM +0100, Richard Sandiford wrote:
> Spencer Abson writes:
> > @@ -27292,10 +27291,16 @@ aarch64_emit_sve_invert_fp_cond (rtx target,
> > rtx_code code, rtx pred,
> > void
> > aarch64_expand_sve_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx
> > op1)
> >
Spencer Abson writes:
> @@ -27292,10 +27291,16 @@ aarch64_emit_sve_invert_fp_cond (rtx target,
> rtx_code code, rtx pred,
> void
> aarch64_expand_sve_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx
> op1)
> {
> - machine_mode pred_mode = GET_MODE (target);
>machine_mode data_mode
This patch extends our vec_cmp expander to support partial FP modes.
We use an unnatural predicate mode to govern unpacked FP operations under
flag_trapping_math, so the expansion must handle cases where the comparison's
target and governing predicates have different modes.
While such predicates
