On 7/28/23 00:34, Xiao Zeng wrote:
What I like about yours is it keeps all the logic in riscv.cc rather
than scattering it across riscv.cc and riscv.md.
Yes, when I use enough test cases, I cannot find a concise way to optimize
all test cases. When I enumerated all possible cases in the
On Fri, Jul 28, 2023 at 11:03:00 PM Jeff Law wrote:
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>On 7/28/23 00:34, Xiao Zeng wrote:
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Does that work for you?
>>> I'm going to look at 3/5 today pretty closely. Exposing zicond to
>>> movcc is something we had implemented inside Ventana and I want to
>>> compare/contrast your
On 7/28/23 00:34, Xiao Zeng wrote:
Does that work for you?
I'm going to look at 3/5 today pretty closely. Exposing zicond to
movcc is something we had implemented inside Ventana and I want to
compare/contrast your work with ours.
What a coincidence!
Zicond is a direct descendant of xvent
On Thu, Jul 27, 2023 at 10:43:00 PM Jeff Law wrote:
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>On 7/27/23 02:43, Xiao Zeng wrote:
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>> 2. According to your opinions, I have modified the code, but out of caution
>> for upstream, I conducted a complete regression tests on patch V2, which took
>> some time. I was unable to reply to
On 7/27/23 02:43, Xiao Zeng wrote:
2. According to your opinions, I have modified the code, but out of caution
for upstream, I conducted a complete regression tests on patch V2, which took
some time. I was unable to reply to emails and upload patch V2 in a timely
manner.
Sorry to have waste
On Wed, Jul 26, 2023 at 01:51:00 AM Jeff Law wrote:
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>On 7/19/23 04:11, Xiao Zeng wrote:
>> Hi all RISC-V folks:
>>
>> This series of patches completes support for the riscv architecture's
>> Zicond standard extension instruction set.
>>
>> Currently, Zicond is in a frozen state.
>>
>> See t
On 7/19/23 04:11, Xiao Zeng wrote:
Hi all RISC-V folks:
This series of patches completes support for the riscv architecture's
Zicond standard extension instruction set.
Currently, Zicond is in a frozen state.
See the Zicond specification for details:
https://github.com/riscv/riscv-zicond/re
Hi all RISC-V folks:
This series of patches completes support for the riscv architecture's
Zicond standard extension instruction set.
Currently, Zicond is in a frozen state.
See the Zicond specification for details:
https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1
