回复：[PATCH 0/4] RISC-V: Add new segment load/store intrinsics for xtheadvector

Hello! Actually the T-head segment load/store instructions and intrinsics is different from standard vector instruction and intrinsics. In doc https://github.com/XUANTIE-RV/thead-extension-spec/edit/master/xtheadvector/intrinsics.adoc

Re: [PATCH 0/4] RISC-V: Add new segment load/store intrinsics for xtheadvector

Hi Yunze: I thought the T-head vector should just reuse segments load/store pattern from standard vector instruction is enough and then adjust the output name at th_asm_output_opcode , do you have a good reason why we need to add those patterns for T-head vector again? I am really concerned about

[PATCH 0/4] RISC-V: Add new segment load/store intrinsics for xtheadvector

From: Yunze Zhu This series add xtheadvector-specific segment load/store intrinsics support, including: [1/4] xtheadvector unit stride segment load/store intrinsics, [2/4] xtheadvector stride segment load/store intrinsics, [3/4] xtheadvector indexed stride segment load/store intrinsics, [4/4] xt