On Wed, Jul 26, 2017 at 03:02:15PM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Wed, Jul 26, 2017 at 12:24:17AM -0400, Michael Meissner wrote:
> > * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
> > -mvsx-small-integer option.
> > (ISA_3_0_MASKS_IEEE): Likewise.
>
On Wed, Jul 26, 2017 at 12:28:02AM -0400, Michael Meissner wrote:
> And not only the patches to the compiler, I forgot to include the testsuite
> patches:
>
> [gcc/testsuite]
> 2017-07-25 Michael Meissner
>
> * gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
> option.
>
Hi Mike,
On Wed, Jul 26, 2017 at 12:24:17AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
> -mvsx-small-integer option.
> (ISA_3_0_MASKS_IEEE): Likewise.
> (POWERPC_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
> @
And not only the patches to the compiler, I forgot to include the testsuite
patches:
[gcc/testsuite]
2017-07-25 Michael Meissner
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powe
I forgot to include the patch for these changes:
[gcc]
2017-07-25 Michael Meissner
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs600
Next up, the elimination of the -mvsx-small-integer option. This patch is a
little more complex than the previous patches. The -mvsx-small-integer was set
with -mpower8-vector or -mcpu=power8, and it would enable SImode to go into
vector registers. While power7 had the instructions to support 32
