Re: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Tamar Christina writes: >> -Original Message- >> From: Richard Sandiford >> Sent: Friday, November 18, 2022 9:30 AM >> To: Tamar Christina >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw >> ; Marcus Shawcroft >> ; Kyrylo Tkachov &g

RE: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

> -Original Message- > From: Richard Sandiford > Sent: Friday, November 18, 2022 9:30 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw > ; Marcus Shawcroft > ; Kyrylo Tkachov > Subject: Re: [PATCH]AArch64 Fix vector re-interpretatio

Re: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Richard Sandiford via Gcc-patches writes: > Tamar Christina writes: >> Hi All, >> >> While writing a patch series I started getting incorrect codegen out from >> VEC_PERM on partial struct types. >> >> It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS >> implementation

Re: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Tamar Christina writes: > Hi All, > > While writing a patch series I started getting incorrect codegen out from > VEC_PERM on partial struct types. > > It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS > implementation has a slight bug in it. The hook only checked for

[PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Hi All, While writing a patch series I started getting incorrect codegen out from VEC_PERM on partial struct types. It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS implementation has a slight bug in it. The hook only checked for SIMD to Partial but never Partial to