Re: [PATCH]AArch64 Extend umov and sbfx patterns.

Tamar Christina writes: > Hi, > >> > --- a/gcc/config/aarch64/aarch64-simd.md >> > +++ b/gcc/config/aarch64/aarch64-simd.md >> > @@ -4259,7 +4259,7 @@ (define_insn >> "*aarch64_get_lane_zero_extend" >> > ;; Extracting lane zero is split into a simple move when it is >> > between SIMD ;; register

RE: [PATCH]AArch64 Extend umov and sbfx patterns.

Hi, > > --- a/gcc/config/aarch64/aarch64-simd.md > > +++ b/gcc/config/aarch64/aarch64-simd.md > > @@ -4259,7 +4259,7 @@ (define_insn > "*aarch64_get_lane_zero_extend" > > ;; Extracting lane zero is split into a simple move when it is > > between SIMD ;; registers or a store. > > (define_insn_an

Re: [PATCH]AArch64 Extend umov and sbfx patterns.

Tamar Christina writes: > Hi All, > > Our zero and sign extend and extract patterns are currently very limited and > only work for the original register size of the instructions. i.e. limited by > GPI patterns. However these instructions extract bits and extend. This means > that any register si

[PATCH]AArch64 Extend umov and sbfx patterns.

Hi All, Our zero and sign extend and extract patterns are currently very limited and only work for the original register size of the instructions. i.e. limited by GPI patterns. However these instructions extract bits and extend. This means that any register size can be used as an input as long a