On Thu, Oct 25, 2018 at 9:10 AM H.J. Lu wrote:
>
> On 10/24/18, Uros Bizjak wrote:
> > On Wed, Oct 24, 2018 at 1:51 AM H.J. Lu wrote:
> >>
> >> Hi Uros,
> >>
> >> Can you take a look at this?
> >
> > Many pmov(s|z)x instructions with memory operands are modelled in a wrong
> > way.
> >
> > For e
eg, which will disable x87 registers.
>
Since vectorizer works only with XMM and YMM registers, wee can't
change existing patterns. As you pointed out that V8QI might trigger
MMX registers. New patterns must match the existing patterns. Otherwise
combiner won't work. This is the
On Sun, Sep 30, 2018 at 1:53 AM Marc Glisse wrote:
>
> On Sat, 29 Sep 2018, H.J. Lu wrote:
>
> > Add pmovzx/pmovsx patterns with SI and DI operands for pmovzx/pmovsx
> > instructions which only read the low 4 or 8 bytes from the source.
>
> Hello,
>
> I am wondering a few things (these are questio
On Sat, 29 Sep 2018, H.J. Lu wrote:
Add pmovzx/pmovsx patterns with SI and DI operands for pmovzx/pmovsx
instructions which only read the low 4 or 8 bytes from the source.
Hello,
I am wondering a few things (these are questions, I am not asking for
changes):
Should we change the builtin an
Add pmovzx/pmovsx patterns with SI and DI operands for pmovzx/pmovsx
instructions which only read the low 4 or 8 bytes from the source.
gcc/
PR target/87317
* config/i386/sse.md (*sse4_1_v8qiv8hi2): New
pattern.
(*sse4_1_v4qiv4si2): Likewise.
(*sse4_1_v4hiv
