Re: [PATCH] vect: Pattern-matched calls in reduction chains

On Mon, 2020-01-27 at 17:02 +, Richard Sandiford wrote: > gcc.dg/pr56350.c started ICEing for SVE in GCC 10 because we > pattern-matched a division reduction: > > a /= 8; > > into a signed shift with division semantics: > > ... = IFN_SDIV_POW2 (..., 3); > > whereas the reduction

[PATCH] vect: Pattern-matched calls in reduction chains

gcc.dg/pr56350.c started ICEing for SVE in GCC 10 because we pattern-matched a division reduction: a /= 8; into a signed shift with division semantics: ... = IFN_SDIV_POW2 (..., 3); whereas the reduction code expected it still to be a gassign. One fix would be to check for a reduct