On 6/27/25 7:59 AM, Oleg Endo wrote:
On Fri, 2025-06-27 at 10:51 -0300, Raphael Moreira Zinsly wrote:
A right shift of 31 will become 0 or 1, this can be checked for
treg_set_expr_not_const01 to avoid matching addc_t_r as this
can expand to a 3 insn sequence instead.
This improves tests 023
On Fri, 2025-06-27 at 10:51 -0300, Raphael Moreira Zinsly wrote:
> A right shift of 31 will become 0 or 1, this can be checked for
> treg_set_expr_not_const01 to avoid matching addc_t_r as this
> can expand to a 3 insn sequence instead.
> This improves tests 023 to 026 from gcc.target/sh/pr54236-
A right shift of 31 will become 0 or 1, this can be checked for
treg_set_expr_not_const01 to avoid matching addc_t_r as this
can expand to a 3 insn sequence instead.
This improves tests 023 to 026 from gcc.target/sh/pr54236-2.c, e.g.:
test_023:
shllr5
mov #0,r1
mov r4,r0
rts
addcr1,
