Re: Ping ^ 3: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-09-16 Thread Xionghu Luo via Gcc-patches
On 2021/9/15 21:11, David Edelsohn wrote: Hi, Xionhu Should "altivec_vsel2" .. 3 .. 4 be "*altivec_vsel2", etc. because they are combiner patterns and never referenced by name? Only the first, named pattern is referenced by the builtin code. Thanks, updated the patchset with Segher's revie

Re: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-09-15 Thread Segher Boessenkool
Hi! Please do not send patches as attachments to replies. Each patch (or patch series) starts its own thread. New versions of patches (or patch series) are new threads. > From: Xionghu Luo > Date: Tue, 27 Apr 2021 01:07:25 -0500 > Subject: [PATCH 1/2] rs6000: Fix wrong code generation for vec_

Re: Ping ^ 3: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-09-15 Thread David Edelsohn via Gcc-patches
Hi, Xionhu Should "altivec_vsel2" .. 3 .. 4 be "*altivec_vsel2", etc. because they are combiner patterns and never referenced by name? Only the first, named pattern is referenced by the builtin code. Other than that question / suggestion, this patch is okay. Please coordinate with Bill and his

Re: Ping ^ 3: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-09-15 Thread Xionghu Luo via Gcc-patches
Ping^3, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/9/6 08:52, Xionghu Luo via Gcc-patches wrote: Ping^2, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/6/30 09:42, Xionghu Luo via Gcc-patches wrote: Gentle ping, thanks.

Ping ^ 2: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-09-05 Thread Xionghu Luo via Gcc-patches
Ping^2, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/6/30 09:42, Xionghu Luo via Gcc-patches wrote: Gentle ping, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/5/14 14:57, Xionghu Luo via Gcc-patches wrote: Hi, On 2021/5/13

Ping: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-06-29 Thread Xionghu Luo via Gcc-patches
Gentle ping, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/5/14 14:57, Xionghu Luo via Gcc-patches wrote: Hi, On 2021/5/13 18:49, Segher Boessenkool wrote: Hi! On Fri, Apr 30, 2021 at 01:32:58AM -0500, Xionghu Luo wrote: The vsel instruction is a bit-wise s

Ping: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-06-06 Thread Xionghu Luo via Gcc-patches
Gentle ping, thanks. https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570333.html On 2021/5/14 14:57, Xionghu Luo via Gcc-patches wrote: Hi, On 2021/5/13 18:49, Segher Boessenkool wrote: Hi! On Fri, Apr 30, 2021 at 01:32:58AM -0500, Xionghu Luo wrote: The vsel instruction is a bit-wise s

Re: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-05-13 Thread Xionghu Luo via Gcc-patches
Hi, On 2021/5/13 18:49, Segher Boessenkool wrote: Hi! On Fri, Apr 30, 2021 at 01:32:58AM -0500, Xionghu Luo wrote: The vsel instruction is a bit-wise select instruction. Using an IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being generated in the combine pass. Per eleme

Re: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-05-13 Thread Segher Boessenkool
Hi! On Fri, Apr 30, 2021 at 01:32:58AM -0500, Xionghu Luo wrote: > The vsel instruction is a bit-wise select instruction. Using an > IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code > being generated in the combine pass. Per element selection is a > subset of per bit-wise selec

*Ping*: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-05-12 Thread Xionghu Luo via Gcc-patches
On 2021/4/30 14:32, Xionghu Luo wrote: The vsel instruction is a bit-wise select instruction. Using an IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being generated in the combine pass. Per element selection is a subset of per bit-wise selection,with the patch the patter

[PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613]

2021-04-29 Thread Xionghu Luo via Gcc-patches
The vsel instruction is a bit-wise select instruction. Using an IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being generated in the combine pass. Per element selection is a subset of per bit-wise selection,with the patch the pattern is written using bit operations. But ther