Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On 7/26/24 12:07 PM, Carl Love wrote: > On 7/24/24 11:47 AM, Segher Boessenkool wrote: > +/* { dg-do run { target { int128 } && { power10_hw } } } */ Everything power10 is int128 always. >>> OK, so don't need the power10_hw. Changed to just int128 for the target: >> No, the other way aro

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Segher: On 7/24/24 11:47 AM, Segher Boessenkool wrote: Hi! On Wed, Jul 24, 2024 at 11:38:11AM -0700, Carl Love wrote: On 7/24/24 10:03 AM, Segher Boessenkool wrote: So much manual stuff needed, sigh. On Fri, Jul 19, 2024 at 01:04:12PM -0700, Carl Love wrote: gcc/ChangeLog:     * config/rs6

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Peter, Segher: On 7/23/24 2:26 PM, Peter Bergner wrote: On 7/19/24 3:04 PM, Carl Love wrote: diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 5af9bf920a2..2a18ee44526 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -878,9 +878,9 @@ (

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Kewen: On 7/25/24 1:21 AM, Kewen.Lin wrote: Hi Carl, Some minor comments are inlined on top of Segher's and Peter's comments. on 2024/7/20 04:04, Carl Love wrote: GCC developers: The following patch adds the int128 varients to the existing overloaded built-ins vec_sld, vec_sldb, vec_sldw, v

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Hi Carl, Some minor comments are inlined on top of Segher's and Peter's comments. on 2024/7/20 04:04, Carl Love wrote: > GCC developers: > > The following patch adds the int128 varients to the existing overloaded > built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, > v

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Hi! On Wed, Jul 24, 2024 at 11:38:11AM -0700, Carl Love wrote: > On 7/24/24 10:03 AM, Segher Boessenkool wrote: > >So much manual stuff needed, sigh. > > > >On Fri, Jul 19, 2024 at 01:04:12PM -0700, Carl Love wrote: > >>gcc/ChangeLog: > >>     * config/rs6000/altivec.md (vsdb_): Change > >>     de

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Segher: Thanks for the review, a few questions... On 7/24/24 10:03 AM, Segher Boessenkool wrote: Hi! So much manual stuff needed, sigh. On Fri, Jul 19, 2024 at 01:04:12PM -0700, Carl Love wrote: gcc/ChangeLog:     * config/rs6000/altivec.md (vsdb_): Change     define_insn iterator to VEC_I

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On Wed, Jul 24, 2024 at 12:16:33PM -0500, Peter Bergner wrote: > > On 7/24/24 12:03 PM, Segher Boessenkool wrote: > >> +/* { dg-options "-mdejagnu-cpu=power10 -save-temps" } */ > > > > Why the -save-temps? Always document it if you want that for something, > > but never put it in the testcase if

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On Wed, Jul 24, 2024 at 12:12:05PM -0500, Peter Bergner wrote: > On 7/24/24 12:06 PM, Segher Boessenkool wrote: > I thought we always wanted the predicate to match the constraint being used? Predicates and constraints have different purposes, and are used at different times (typically). Everythin

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On 7/24/24 12:03 PM, Segher Boessenkool wrote: >> +/* { dg-options "-mdejagnu-cpu=power10 -save-temps" } */ > > Why the -save-temps? Always document it if you want that for something, > but never put it in the testcase if not. A leftover from development? I can answer this one. :-). Since th

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On 7/24/24 12:06 PM, Segher Boessenkool wrote: > On Tue, Jul 23, 2024 at 04:26:43PM -0500, Peter Bergner wrote: >> On 7/19/24 3:04 PM, Carl Love wrote: >>> (define_insn "vsdb_" >>> - [(set (match_operand:VI2 0 "register_operand" "=v") >>> - (unspec:VI2 [(match_operand:VI2 1 "register_operand" "v"

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On Tue, Jul 23, 2024 at 04:26:43PM -0500, Peter Bergner wrote: > On 7/19/24 3:04 PM, Carl Love wrote: > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > > index 5af9bf920a2..2a18ee44526 100644 > > --- a/gcc/config/rs6000/altivec.md > > +++ b/gcc/config/rs6000/altivec.md

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Hi! So much manual stuff needed, sigh. On Fri, Jul 19, 2024 at 01:04:12PM -0700, Carl Love wrote: > gcc/ChangeLog: >     * config/rs6000/altivec.md (vsdb_): Change >     define_insn iterator to VEC_IC. >From VI2 (a nothing-saying name) to VEC_IC (also a nonsensical name). Maybe VEC_IC should ha

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Peter: On 7/23/24 2:26 PM, Peter Bergner wrote: On 7/19/24 3:04 PM, Carl Love wrote: diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 5af9bf920a2..2a18ee44526 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -878,9 +878,9 @@ (define_i

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

On 7/19/24 3:04 PM, Carl Love wrote: > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index 5af9bf920a2..2a18ee44526 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -878,9 +878,9 @@ (define_int_attr SLDB_lr [(UNSPEC_SLDB "l") > (def

[PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

GCC developers: The following patch adds the int128 varients to the existing overloaded built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro.  These varients were requested by Steve Munroe. The patch has been tested on a Power 10 system with no regressions. Ple