Richard Biener writes:
> On Thu, 5 Dec 2024, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Fri, 29 Nov 2024, Jakub Jelinek wrote:
>> >
>> >> On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote:
>> >> > For a TSVC testcase we see failed register coalescing due to a
>> >>
On Thu, 5 Dec 2024, Richard Sandiford wrote:
> Richard Biener writes:
> > On Fri, 29 Nov 2024, Jakub Jelinek wrote:
> >
> >> On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote:
> >> > For a TSVC testcase we see failed register coalescing due to a
> >> > different schedule of GIMPLE .F
Richard Biener writes:
> On Fri, 29 Nov 2024, Jakub Jelinek wrote:
>
>> On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote:
>> > For a TSVC testcase we see failed register coalescing due to a
>> > different schedule of GIMPLE .FMA and stores fed by it. This
>> > can be mitigated by ma
On Fri, 29 Nov 2024, Jakub Jelinek wrote:
> On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote:
> > For a TSVC testcase we see failed register coalescing due to a
> > different schedule of GIMPLE .FMA and stores fed by it. This
> > can be mitigated by making direct internal functions
On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote:
> For a TSVC testcase we see failed register coalescing due to a
> different schedule of GIMPLE .FMA and stores fed by it. This
> can be mitigated by making direct internal functions participate
> in TER - given we're using more and m
For a TSVC testcase we see failed register coalescing due to a
different schedule of GIMPLE .FMA and stores fed by it. This
can be mitigated by making direct internal functions participate
in TER - given we're using more and more of such functions to
expose target capabilities it seems to be a nat
