On Thu, Jul 8, 2021 at 2:04 PM Richard Sandiford via Gcc-patches
wrote:
>
> -msve-vector-bits=128 causes the AArch64 port to list 128-bit Advanced
> SIMD as the first-choice mode for vectorisation, with SVE being used for
> things that Advanced SIMD can't handle as easily. However, ifcvt would
>
-msve-vector-bits=128 causes the AArch64 port to list 128-bit Advanced
SIMD as the first-choice mode for vectorisation, with SVE being used for
things that Advanced SIMD can't handle as easily. However, ifcvt would
not then try to use SVE's predicated FP arithmetic, leading to tests
like TSVC Cont
