Re: [PATCH] expand: Fix ICE in store_bit_field_using_insv [PR93235]

2021-03-04 Thread Jeff Law via Gcc-patches
On 3/4/21 2:11 AM, Jakub Jelinek wrote: > Hi! > > The following testcase ICEs on aarch64. The problem is that > op0 is (subreg:HI (reg:HF ...) 0) and because we can't create a SUBREG of a > SUBREG and aarch64 doesn't have HImode insv, only SImode insv, > store_bit_field_using_insv tries to crea

[PATCH] expand: Fix ICE in store_bit_field_using_insv [PR93235]

2021-03-04 Thread Jakub Jelinek via Gcc-patches
Hi! The following testcase ICEs on aarch64. The problem is that op0 is (subreg:HI (reg:HF ...) 0) and because we can't create a SUBREG of a SUBREG and aarch64 doesn't have HImode insv, only SImode insv, store_bit_field_using_insv tries to create (subreg:SI (reg:HF ...) 0) which is not valid for t