> -Original Message-
> From: Alex Coplan
> Sent: 17 May 2021 17:29
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Subject: Re: [PATCH] arm: Fix ICEs with compare-and-swap and -
> march=arm
hnan ; Kyrylo
> > Tkachov
> > Subject: Re: [PATCH] arm: Fix ICEs with compare-and-swap and -
> > march=armv8-m.base [PR99977]
> >
> > Ping
> >
> > On 15/04/2021 15:39, Alex Coplan via Gcc-patches wrote:
> > > Hi all,
> > >
> > >
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: 27 April 2021 14:14
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: Re: [PATCH] arm: Fix ICEs with compare-and-swap and -
>
Ping
On 15/04/2021 15:39, Alex Coplan via Gcc-patches wrote:
> Hi all,
>
> The PR shows two ICEs with __sync_bool_compare_and_swap and
> -mcpu=cortex-m23 (equivalently, -march=armv8-m.base): one in LRA and one
> later on, after the CAS insn is split.
>
> The LRA ICE occurs because the
> @atomic_
Hi all,
The PR shows two ICEs with __sync_bool_compare_and_swap and
-mcpu=cortex-m23 (equivalently, -march=armv8-m.base): one in LRA and one
later on, after the CAS insn is split.
The LRA ICE occurs because the
@atomic_compare_and_swap_1 pattern attempts to tie
two output operands together (opera
