> + GET_MODE_UNIT_SIZE (mode));
>>>
>>> Perhaps we should add yet another overload of aarch64_ptrue_reg that
>>> takes the data mode as a second argument. The implementation could
>>> be something like:
>>>
>>> /* Return a
or an SVE vector.
>> If it's an N-byte scalar or an Advanced SIMD vector, the first N bits
>> of the predicate will be active and the rest will be inactive.
>> If DATA_MODE is an SVE mode, every bit of the predicate will be active. */
>> static rtx
>> aarc
Hi Richard,
Thanks for reviewing this!
I’ve made the suggested changes and added the aarch64_ptrue_reg overload.
Thank you for providing the implementation for this, I have added you
as a co-author for the patch, hope that works :)
Best,
Soumya
> On 5 Dec 2024, at 10:08 PM, Richard Sandiford
Soumya AR writes:
> The ASRD instruction on SVE performs an arithmetic shift right by an immediate
> for divide.
>
> This patch enables the use of ASRD with Neon modes.
>
> For example:
>
> int in[N], out[N];
>
> void
> foo (void)
> {
> for (int i = 0; i < N; i++)
> out[i] = in[i] / 4;
> }
>
The ASRD instruction on SVE performs an arithmetic shift right by an immediate
for divide.
This patch enables the use of ASRD with Neon modes.
For example:
int in[N], out[N];
void
foo (void)
{
for (int i = 0; i < N; i++)
out[i] = in[i] / 4;
}
compiles to:
ldr q31, [x1, x0]
