On Fri, Jul 4, 2025 at 9:18 AM Richard Sandiford
wrote:
>
> Lowpart subregs are generally disallowed on big-endian SVE vector
> registers, since the first memory element is stored at the least
> significant end of the register, rather than the most significant end.
> (See the comment at the head o
Lowpart subregs are generally disallowed on big-endian SVE vector
registers, since the first memory element is stored at the least
significant end of the register, rather than the most significant end.
(See the comment at the head of aarch64-sve.md for details,
and aarch64_modes_compatible_p for th
