On Fri, 17 Mar 2017 15:52:54 PDT (-0700), Palmer Dabbelt wrote:
> The RISC-V memory model is still in the process of being formally
> specified, so for now we're going to be safe and add the I/O bits to
> userspace fences because there's no way to know if userspace is touching
> memory-mapped I/O r
The RISC-V memory model is still in the process of being formally
specified, so for now we're going to be safe and add the I/O bits to
userspace fences because there's no way to know if userspace is touching
memory-mapped I/O regions at compile time.
This will have no impact on existing microarchi
