Waterman
Subject: [EXTERNAL]RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget
On Thu, 08 May 2025 08:53:18 PDT (-0700), ukala...@mips.com wrote:
> Hi All ,
>
> We have couple of patch series that enables the P8700 tune for RISCV core to
> upstream for GCC mainline.
>
> It will be goo
e.com; Jesse Huang ;
and...@sifive.com
Subject: Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
Hi @Jeff Law and @pal...@dabbelt.com ,
Please do needful by reviewing the below changes and helps us to upstream the
same .
Thank you
~U
-Original Message-
From: Umesh Kalappa
Sent: 29 April 20
-patches@gcc.gnu.org;
pal...@dabbelt.com
Cc: kito.ch...@sifive.com; Jesse Huang ;
and...@sifive.com
Subject: Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
Hi @Jeff Law and @pal...@dabbelt.com ,
Please do needful by reviewing the below changes and helps us to upstream the
same .
Thank you
~U
; Jesse Huang ;
pal...@dabbelt.com; and...@sifive.com
Subject: RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
Hi all,
Here is the updated patch that address some of the @Jeff Law comments .
P8700 don't have a vector engine and we support the insns type till
https://github.co
/
+ true, /* use_divmod_expansion */
+ false, /* overlap_op_by_pieces */
+ RISCV_FUSE_NOTHING, /* fusible_ops */
+ NULL, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
org
Cc: kito.ch...@sifive.com; Jesse Huang ;
pal...@dabbelt.com; and...@sifive.com
Subject: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
On 4/11/25 6:02 AM, Umesh Kalappa wrote:
> This is the first patch from the two-patch series, where configured
> gcc for P8700 micro architecture
On 4/11/25 6:02 AM, Umesh Kalappa wrote:
This is the first patch from the two-patch series, where configured gcc for
P8700 micro architecture in the first patch and
Tested with dejagnu riscv.exp tests for --mtune=mips-p8700.
P8700 is a high-performance processor from MIPS by extending RIS
This is the first patch from the two-patch series, where configured gcc for
P8700 micro architecture in the first patch and
Tested with dejagnu riscv.exp tests for --mtune=mips-p8700.
P8700 is a high-performance processor from MIPS by extending RISCV. The
following changes enable P8700 proces
...@dabbelt.com; and...@sifive.com; j...@sifive.com
Subject: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.
[You don't often get email from kito.ch...@gmail.com. Learn why this is
important at https://aka.ms/LearnAboutSenderIdentification ]
Could you break this patch into two pieces:
1) Ad
Could you break this patch into two pieces:
1) Add new extensions.
2) Add new core (for -mcpu), pipeline model and cost model
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a
> 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,24 @@
> +2025-04-09 Umesh K
P8700 is a high-performance processor from MIPS by extending RISCV with the
MIPS custom instructions.
Tested with dejagnu riscv.exp tests for --mtune=mips-p8700.
Please refer @ https://mips.com/products/hardware/p8700/
---
gcc/ChangeLog| 21 +++
gcc/common/confi
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