On Fri, 13 Oct 2023, Juzhe-Zhong wrote:
> Like ARM SVE and GCN, add RVV.
Adding RVV when SVE or GCN is already there looks obvious to me, these
kind of changes are pre-approved. No need for all the noise.
Thanks,
Richard.
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-pr69907.c: Ad
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-13 14:01
To: Juzhe-Zhong
CC: GCC Patches; Jeff Law; Richard Biener
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
LGTM
Juzhe-Zhong 於 2023年10月12日 週四 22:45 寫道:
Like ARM SVE and GCN, add RVV
LGTM
Juzhe-Zhong 於 2023年10月12日 週四 22:45 寫道:
> Like ARM SVE and GCN, add RVV.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
>
> ---
> gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/te
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
b/gcc/testsuite/gcc.dg/vect