Re: [PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

On 12/19/24 12:56 AM, Robin Dapp wrote: From: Yunze Zhu Fix a bug th.vsetvli generates from vext_x_v with an imm operand, which reports illegal operand. This patch fix this by replacing imm operand with reg operand in th.vsetvli. LGTM but you might want to add check force_vector_length_ope

Re: [PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

> - avl = GEN_INT (0); > + avl = TARGET_XTHEADVECTOR ? gen_rtx_REG(Pmode, 0) : GEN_INT (0); Ah, the CI linter complains about a missing space after gen_rtx_REG. -- Regards Robin

Re: [PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

> From: Yunze Zhu > > Fix a bug th.vsetvli generates from vext_x_v with an imm operand, > which reports illegal operand. This patch fix this by replacing > imm operand with reg operand in th.vsetvli. LGTM but you might want to add check force_vector_length_operand which likely needs similar handl

[PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

From: Yunze Zhu Fix a bug th.vsetvli generates from vext_x_v with an imm operand, which reports illegal operand. This patch fix this by replacing imm operand with reg operand in th.vsetvli. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: gcc/testsuite/ChangeLog: * gcc.target/ri