Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

On 6/5/25 2:30 AM, Umesh Kalappa wrote: Thank you @Jeff Law   for the initial comments ,yes will update the ChangeLog accordingly and typo fix and >>My biggest concern is overall structure of riscv_expand_conditional_move.  I kind of get the sense >>that we ne

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Thank you @Jeff Law for the initial comments ,yes will update the ChangeLog accordingly and typo fix and >>My biggest concern is overall structure of riscv_expand_conditional_move. I kind of get the sense >>that we need to refactor operand canonicalization into its own routine, >>then have two

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

On 5/27/25 5:06 AM, Umesh Kalappa wrote: The P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instruction and the following changes are added to enable the conditional move support from mips No regressions are found for "runtest --tool gcc --target_boa

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Hi @Jeff Law , @pal...@dabbelt.com and all , Please can you pass your comments on the below changes ,thank you ~U On Tue, May 27, 2025 at 4:36 PM Umesh Kalappa wrote: > The P8700 is a high-performance processor from MIPS by extending RISCV with > the MIPS custom instruction and the followin

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Hi all, Sorry for the noise ,looks like patch was truncated and will be sending a new email with proper patch for the same. Thank you and again my apologies for the noise. ~U On Tue, May 27, 2025 at 3:41 PM Umesh Kalappa wrote: > The P8700 is a high-performance processor from MIPS by extending

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

The P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instruction and the following changes are added to enable the conditional move support from mips No regressions are found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtu

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

The P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instruction and the following changes are added to enable the conditional move support from mips. No regression found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=m