Re: [PATCH] RISC-V: xtheadmemidx: Disable pre/post-modify addressing if RVV is enabled

On Wed, Jul 24, 2024 at 3:57 PM Jeff Law wrote: > > > > On 7/24/24 7:31 AM, Christoph Müllner wrote: > > When enabling XTheadMemIdx, we enable the pre- and post-modify > > addressing modes in the RISC-V backend. > > Unfortunately, the auto_inc_dec pass will then attempt to utilize > > this feature

Re: [PATCH] RISC-V: xtheadmemidx: Disable pre/post-modify addressing if RVV is enabled

On 7/24/24 7:31 AM, Christoph Müllner wrote: When enabling XTheadMemIdx, we enable the pre- and post-modify addressing modes in the RISC-V backend. Unfortunately, the auto_inc_dec pass will then attempt to utilize this feature regardless of the mode class (i.e. scalar or vector). The assumptio

Re: [PATCH] RISC-V: xtheadmemidx: Disable pre/post-modify addressing if RVV is enabled

LGTM :) On Wed, Jul 24, 2024 at 9:31 PM Christoph Müllner wrote: > > When enabling XTheadMemIdx, we enable the pre- and post-modify > addressing modes in the RISC-V backend. > Unfortunately, the auto_inc_dec pass will then attempt to utilize > this feature regardless of the mode class (i.e. scala

[PATCH] RISC-V: xtheadmemidx: Disable pre/post-modify addressing if RVV is enabled

When enabling XTheadMemIdx, we enable the pre- and post-modify addressing modes in the RISC-V backend. Unfortunately, the auto_inc_dec pass will then attempt to utilize this feature regardless of the mode class (i.e. scalar or vector). The assumption seems to be, that an enabled addressing mode for