subject:"\[PATCH\] RISC\-V\: Support cond vmulh.vv and vmulu.vv"

Re: [PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-13 Thread Lehua Ding

Committed, thanks Kito. On 2023/9/13 16:50, Kito Cheng wrote: LGTM, thanks :) On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote: This patch adds combine patterns to combine vmulh[u].vv + vcond_mask to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend currently. We will send a

Re: [PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-13 Thread Kito Cheng via Gcc-patches

LGTM, thanks :) On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote: > > This patch adds combine patterns to combine vmulh[u].vv + vcond_mask > to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend > currently. We will send another patch to take this issue. > > gcc/ChangeLog: > >

[PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

2023-09-12 Thread Lehua Ding

This patch adds combine patterns to combine vmulh[u].vv + vcond_mask to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend currently. We will send another patch to take this issue. gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_3_highpart): New combine pattern.