Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, June 4, 2023 9:38 PM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ;
kito.cheng ; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
LGTM too, thanks
On Sun, Jun 4, 2023 at
LGTM too, thanks
On Sun, Jun 4, 2023 at 3:36 PM 钟居哲 wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-04 15:19
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Support RVV FP16
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-04 15:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
From: Pan Li
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for
From: Pan Li
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions
vfwcvt.f.f.v
vfncvt.f.f.w
Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.
Signed-off-by: Pan Li
g
