On 3/28/24 4:31 AM, demin.han wrote:
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in spill.
This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.
Tested on RV64 and no regression.
OK，I will spilt them.
Thanks.
From: juzhe.zh...@rivai.ai
Sent: 2024年3月28日 19:11
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
; Robin Dapp
Subject: 回复: RE: [PATCH] RISC-V: Refine the condition for add additional vars
in RVV cost model
OK. It's an obvious fix b
yalaw
; Robin Dapp
Subject: Re: [PATCH] RISC-V: Refine the condition for add additional vars in
RVV cost model
Thanks a lot for trying to optimize the dynamic LMUL cost model.
The need_additional_vector_vars_p looks good to me.
But
- = (*program_points_per_bb.get (bb)).length (
ivai.ai>;
kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>;
jeffreyalaw<mailto:jeffreya...@gmail.com>; rdapp.gcc<mailto:rdapp....@gmail.com>
Subject: [PATCH] RISC-V: Refine the condition for add additional vars in RVV
cost model
The adjacent_
...@rivai.ai
From: demin.han
Date: 2024-03-28 18:31
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Refine the condition for add additional vars in RVV
cost model
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in spill.
This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.
Tested on RV64 and no regression.
PR target/114506
gcc/ChangeLog:
