On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the mask
register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> According to RVV ISA:
> 14. Vector Reduction Operations
>
> "The destination vector regi
On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the mask
register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
From: Ju-Zhe Zhong
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the
mask register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
---
gcc/config/riscv/vector.md | 96 +++
