Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 10/21/23 19:33, Tsukasa OI wrote: Hmm, I generally agree with your opinion and I made a board file for DejaGnu (running qemu-riscv64) to run "make check-gcc RUNTESTFLAGS='--target_board=riscv-sim riscv.exp'" because it already contains many execute tests (and annoys me if I don't do that)

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 2023/10/22 3:04, Jeff Law wrote: > > > On 10/20/23 23:32, Tsukasa OI wrote: >> From: Tsukasa OI >> >> According to the ratified privileged specification (version 20211203), >> it says: >> >>> The hypervisor extension depends on an "I" base integer ISA with 32 x >>> registers (RV32I or RV64I),

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 10/20/23 23:32, Tsukasa OI wrote: From: Tsukasa OI According to the ratified privileged specification (version 20211203), it says: The hypervisor extension depends on an "I" base integer ISA with 32 x registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the la

[PATCH] RISC-V: Prohibit combination of 'E' and 'H'

From: Tsukasa OI According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with