Re: [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

On 8/27/24 3:17 AM, Xianmiao Qu wrote: Currently, in RV32, even with the D extension enabled, the cost of DFmode register moves is still set to 'COSTS_N_INSNS (2)'. This results in the 'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG register moves, leading to the gen

Re: [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

Thank you for your comments. I also think that the description of cost may need further improvement. For example, I noticed that when the destination address of SET is a register, riscv_rtx_costs will always return true, but we haven't covered all scenarios. On Tue, Aug 27, 2024 at 05:42:36PM +08

Re: [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

LGTM, good catch, and I am a little suppressed that we don't handle "case REG" in riscv_rtx_costs...but adding that might disturb too much at once, so this fix is fine for now, and ...and I guess we should improve that in future. On Tue, Aug 27, 2024 at 5:19 PM Xianmiao Qu wrote: > > Currently,

[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

Currently, in RV32, even with the D extension enabled, the cost of DFmode register moves is still set to 'COSTS_N_INSNS (2)'. This results in the 'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG register moves, leading to the generation of many redundant instructions. As