Re: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

On Wed, 04 Sep 2024 15:20:45 PDT (-0700), jeffreya...@gmail.com wrote: On 9/4/24 4:07 PM, Palmer Dabbelt wrote: These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires

Re: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

On 9/4/24 4:07 PM, Palmer Dabbelt wrote: These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires on conditionals from function inputs. Jeff just posed a patch to clean

Re: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

On 9/4/24 4:07 PM, Palmer Dabbelt wrote: These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires on conditionals from function inputs. Jeff just posed a patch to clean

[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires on conditionals from function inputs. Jeff just posed a patch to clean this code up with trips up on the arbitrary x