* Jim Wilson [2019-10-17 14:55:34 -0700]:
> On Thu, Oct 17, 2019 at 7:09 AM Andrew Burgess
> wrote:
> > I'm still working on part 2, I'm hoping to have a revised patch posted
> > by Monday next week.
>
> I started looking at the part 2 patch also. I noticed a problem where
> the NOTE_INSN_EPIL
On Thu, Oct 17, 2019 at 7:09 AM Andrew Burgess
wrote:
> I'm still working on part 2, I'm hoping to have a revised patch posted
> by Monday next week.
I started looking at the part 2 patch also. I noticed a problem where
the NOTE_INSN_EPILOGUE_BEGIN can occur before the
NOTE_INSN_PROLOGUE_END due
* Jim Wilson [2019-10-16 14:04:45 -0700]:
> This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
> This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
> also adds the missing riscv_regno_to_class change.
>
> Tested with cross riscv32-elf and riscv64-li
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
also adds the missing riscv_regno_to_class change.
Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressio
