> On Sep 30, 2024, at 13:58, Kito Cheng wrote:
>
> Hi Yang-Yu:
>
>>
>> Specially, we can reproduce the result on BananaPi-F3 Hardware:
>>
>> Use this GCC branch with my patch:
>> https://github.com/cyyself/gcc/tree/rv_can_inline
>>
>> And compile the coremark on this branch:
>> https://git
Hi Yang-Yu:
>
> Specially, we can reproduce the result on BananaPi-F3 Hardware:
>
> Use this GCC branch with my patch:
> https://github.com/cyyself/gcc/tree/rv_can_inline
>
> And compile the coremark on this branch:
> https://github.com/cyyself/coremark/tree/rva22_v_hotspot
>
> With command `make
> On Sep 30, 2024, at 10:34, Yangyu Chen wrote:
>>
>>
>> On Sep 30, 2024, at 02:49, Jeff Law wrote:
>> On 9/9/24 6:11 AM, Yangyu Chen wrote:
>>> Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
>>> ISA. As a result, certain functions cannot be optimized with inlining
>>> when
> On Sep 30, 2024, at 02:49, Jeff Law wrote:
>
>
>
> On 9/9/24 6:11 AM, Yangyu Chen wrote:
>> Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
>> ISA. As a result, certain functions cannot be optimized with inlining
>> when specific options, such as __attribute__((target("arc
On 9/9/24 6:11 AM, Yangyu Chen wrote:
Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
ISA. As a result, certain functions cannot be optimized with inlining
when specific options, such as __attribute__((target("arch=+v"))) .
This can lead to potential performance issues when bu
Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
ISA. As a result, certain functions cannot be optimized with inlining
when specific options, such as __attribute__((target("arch=+v"))) .
This can lead to potential performance issues when building
retargetable binaries for RISC-V.
T
