Re: [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL

2023-01-26 Thread Kito Cheng via Gcc-patches
committed, thanks. On Tue, Jan 3, 2023 at 9:40 AM wrote: > From: Ju-Zhe Zhong > > Notice that we should used vsetivli zero,4 instead of vsetvli zero,4 > for IMM AVL (0 ~ 31) according to RVV ISA. > > This patch fix vsetivli instruction asm bug. > > gcc/ChangeLog: > > * config/riscv/vect

[PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL

2023-01-02 Thread juzhe . zhong
From: Ju-Zhe Zhong Notice that we should used vsetivli zero,4 instead of vsetvli zero,4 for IMM AVL (0 ~ 31) according to RVV ISA. This patch fix vsetivli instruction asm bug. gcc/ChangeLog: * config/riscv/vector.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vle-co