gt; Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx
> codegen
>
>
> On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > Current expansion of vmsge will make RA produce redundant vmv1r.v.
> >
> > testcas
I can push codes yet. Can you push them for me?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:42
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx
codegen
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
Current expansion of vmsge will make RA produce redundant vmv1r.v.
testcase:
void f1 (void * in, void *out, int32_t x)
{
vbool32_t mask = *(vbool32_t*)in;
asm volatile ("":::"memory");
vint32m1_t v = __riscv_vle
LGTM, but pending this to the GCC 14 queue.
On Wed, Mar 22, 2023 at 8:16 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Current expansion of vmsge will make RA produce redundant vmv1r.v.
>
> testcase:
> void f1 (void * in, void *out, int32_t x)
> {
> vbool32_t mask = *(vbool32_t*)in;
> asm volatil
From: Ju-Zhe Zhong
Current expansion of vmsge will make RA produce redundant vmv1r.v.
testcase:
void f1 (void * in, void *out, int32_t x)
{
vbool32_t mask = *(vbool32_t*)in;
asm volatile ("":::"memory");
vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
vint32m1_t v2 = __riscv_vle32_
